A solid state drive (SSD) is designed to provide reliable and high performance storage of user data across a flash-based memory system containing a host interface controller (such as a Serial Advanced Technology Attachment (SATA)) interface) and a number of memory multi-chip packages (MCPs), where each MCP contains a flash memory controller and a stack of NAND flash dies. The Open NAND Flash Interface (ONFI) protocol provides support for parallel access to multiple NAND dies (or “logical units” (LUNs)) on a single “target” or NAND multi-chip stack on a single shared ONFI channel. In a typical SATA-based SSD application, a central host controller accesses multiple attached devices (targets/NAND device clusters) on each ONFI channel, and across several ONFI channels. Each ONFI target typically controls 2, 4, or 8 NAND dies. Storage management software running on the host controller manages a virtual memory space that is mapped to flash blocks in the physical dies in each of the attached MCP's. The host controller and the storage management software utilize parallel access and efficient usage of the available flash devices to optimize SSD drive performance, endurance, and cost.
In the ONFI standard, the only basic status reporting for a NAND erase, program, or read operation is a single shared pass/fail bit in a status register. On a command-by-command basis, the host reads the pass/fail bit in the status register to see if that particular command has passed or failed. Other industry standard storage interface protocols, such as SCSI or PCIexpress, support more extensive status reporting, as well as target-initiated event reporting. This can be implemented with bus interrupts from a target to the host or by utilizing a “mailbox function” where the target device initiates a bus transaction to write into the host controller's memory space or a shared space in the host memory. However, the ONFI protocol does not support this model.